The present invention relates to a semiconductor integrated circuit device, and particularly to an internal voltage generator which supplies internal source voltage to load circuits such as a memory circuit, a logic circuit, etc.
An internal voltage generator employed in a semiconductor integrated circuit device needs a contrivance on such a circuit that a constant interval source voltage is generated irrespective of a variation in load current.
In a voltage regulator disclosed in, for example, Japanese Unexamined Patent Publication No. 2005-202781 (Patent Document 1), a main group is formed by a first amplifier, a second amplifier, P-MOSFET and a phase compensating capacitor. A sub group is formed by a third amplifier, a dc-component cutting capacitor and P-MOSFET. The sub group based on the third amplifier is capable of reducing the amount of variation in output voltage even though a load current rises at high speed. The second amplifier is used when it is desired to further increase the gain of a signal amplified by the first amplifier.
A voltage generator or generating circuit disclosed in Japanese Unexamined Patent Publication No. 2005-71067 (Patent Document 2) includes an error amplifier having differential amplifier circuits of two stages coupled in tandem, and a control circuit having cascade-coupled inverter circuits. The control circuit performs control as to driving of both differential amplifier circuits or driving of only the differential amplifier circuit of subsequent stage according to a high-low relationship between a gate voltage of a P channel MOSFET for a driver and an operational threshold voltage of each inverter circuit.
Thus, since the gain of the error amplifier becomes high by driving of both the differential amplifier circuits where the operating current of each internal circuit is large, the response to a change in operating state of the internal circuit can be enhanced, and the supply capacity of current to the internal circuit can be improved. Since the differential amplifier circuits are not driven when the operating current of the internal circuit is small, the amount of current consumption in the error amplifier can be suppressed as compared with the case in which the differential amplifier circuits of two stages are always driven.
A constant voltage circuit disclosed in Japanese Unexamined Patent Publication No. 2005-316959 (Patent Document 3) has a first error amplifier made high in dc gain, and a second error amplifier having a fast response characteristic. Control on the operation of an output voltage control transistor is performed with respect to a variation in output voltage by means of the first and second error amplifiers. The first error amplifier is designed to reduce the drain current of an NMOS transistor that forms a constant current source, as small as possible. The second error amplifier is designed to make as large as possible the drain current of the NMOS transistor that forms the constant current source.